Some data storage systems utilize a standby power supply (SPS) which interconnects between a power supply of the data storage system and a main power feed, i.e., AC-line power. If the AC-line power from the main power feed becomes unavailable, the SPS provides DC backup power to the data storage system in place of the AC-line power. The SPS typically provides enough DC backup power to enable the data storage system to dump its cache into non-volatile memory and, if the AC-line power does not return within a predefined amount of time, to further perform an orderly shutdown.
FIG. 1 shows a block diagram of conventional data storage equipment 20 which includes a data storage system 22, an SPS assembly 24, two power supply power pathways 26(1), 26(2) (collectively, power supply power pathways 26), and two SPS communications pathways 28(1), 28(2) (collectively, SPS communications pathways 28). The data storage system 22 includes storage processing circuitry 30 (e.g., multiple storage processors which perform data storage operations on behalf of one or more host computers) and two power supplies 32(1), 32(2) (collectively, power supplies 32). The power supplies 32 are shown immediately adjacent the storage processing circuitry 30 to illustrate a configuration in which the power supplies 32 and the storage processing circuitry 30 reside together in a common enclosure.
As shown in FIG. 1, the SPS assembly 24 includes two SPS units 34(1), 34(2) (collectively, SPS units 34). The SPS unit 34(1) connects to a main power feed 36(1), the power supply power pathway 26(1) leading to the power supply 32(1), and the SPS communications pathway 28(1) leading to the storage processing circuitry 30. Similarly, the SPS unit 34(2) connects to a main power feed 36(2), the power supply power pathway 26(2) leading to the power supply 32(2), and the SPS communications pathway 28(2) leading to the storage processing circuitry 30. The power supply power pathways 26 (i.e., power paths) are separate and independent of the SPS communications pathways 28 (i.e., data signal paths).
As further shown in FIG. 1, each SPS unit 34 includes a controller 38, a set of batteries 40, and an ON/OFF switch 42. In particular, the SPS unit 34(1) includes a controller 38(1), a set of batteries 40(1), and an ON/OFF switch 42(1). Likewise, the SPS unit 34(2) includes a controller 38(2), a set of batteries 40(2), and an ON/OFF switch 42(2). The controllers 38 direct the operation of the SPS units 34. The batteries 40 store backup power for use by the data storage system 22 in the event of a loss of the main power feeds 36(1), 36(2) (collectively, main power feeds 36). The switches 42 enable a user to cutoff power completely to the power supplies 32.
When the power supplies 32 receive AC-line power from the SPS units 34, the power supplies 32 output DC power signals having a first polarity to the storage processing circuitry 30. However, if the power supplies 32 receive backup DC power from the SPS units 34, the power supplies 32 output DC power signals having the opposite polarity to the storage processing circuitry 30. The storage processing circuitry 30 is equipped with polarity detectors 44(1), 44(2) thus enabling the storage processing circuitry 30 to distinguish between a normal situation in which the storage processing circuitry 30 is running on AC-line power from the main power feeds 36, and an abnormal situation in which the storage processing circuitry 30 is running on DC backup power from the batteries 40.
During operation of the data storage equipment 20, the controllers 38 of the SPS units 34 normally supply AC-line power to the data storage system 22 directly from the main power feeds 36, and charge the batteries 40 when necessary. In response to the AC-line power, the storage processing circuitry 30 stores data into and retrieves data from an array of disk drives on behalf of one or more external host computers. Additionally, software running on storage processing circuitry 30 (e.g., a master controller) periodically sends SPS queries and SPS commands to the SPS assembly 24 through the SPS communications pathways in order to obtain SPS operating information and guide the operation of the SPS assembly 24 (e.g., a slave controller). In response to the SPS queries, the controllers 38 of the SPS units 34 provide particular SPS responses back to the data storage system 22 through the SPS communications pathways 28 (e.g., an SPS response identifying an operating state in response to an SPS condition query, an SPS response providing results of a battery test in response to an SPS battery test query, etc.). Furthermore, in response to the SPS commands, the controllers 38 perform particular SPS functions (e.g., an SPS command to test the batteries 40, another SPS command to modify operating parameters, etc.).
If main power (i.e., AC-line power) is lost during operation, the controllers 38 disconnect the main power feeds 36 from the power supply power pathways 26, and instead supply backup power (i.e., DC power) from the batteries 40 to the data storage system 22 through the power supply power pathways 26. Upon detection of this event by the detectors 44(1), 44(2) of the storage processing circuitry 30, the storage processing circuitry 30 begins a fault tolerant procedure which involves dumping its cache out to non-volatile memory and shutting down.
If main power returns to normal before the storage processing circuitry 30 reaches a defined shutdown point, the SPS units 34 switch back to supplying main power through the power supply power pathways 26. In response, the storage processing circuitry 30 is capable resuming normal operation (e.g., write-caching operations).
However, if the storage processing circuitry 30 passes the defined shutdown point and main power has not returned, the storage processing circuitry 30 performs an orderly shutdown and commands the SPS units 34 through the SPS communications pathways 28 to shutdown as well. Once shutdown, the SPS units 34 will return to normal operation upon return of main power.